//this module will account for the awesomeness that is the load stall

/*
20:16= rt

EX/MEM.RegWrite= stage 2 C_Regwrite
Ex/MEM.RegisterRd = RwIn stage 2
ID/EX. RegisterRs = Rs1;
ID/EX. RegisterRt = Rt1
IF/ID.RegisterRS = RaIn
IF/ID.RegisterRr = RbIn

*/

module Hazard_Unit(MemRead, Rs1, Rt1, RaIn, RbIn, NoOp);

// NoOp will be sent through the pipeline 
// as a stall to account for the lw desintation matching the source

input [4:0] Rs1, Rt1, RaIn, RbIn;
input MemRead;

output NoOp;
reg NoOp;

always @(MemRead or Rs1 or Rt1 or RaIn or RbIn)
begin

if (MemRead
    && ((Rs1 == RaIn)
    ||  (Rt1 == RbIn)))
        NoOp = 1;
else 
    NoOp = 0;	
end

endmodule

